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| HN58C256 Series 32768-word x 8-bit Electrically Erasable and Programmable CMOS ROM ADE-203-092G (Z) Rev. 7.0 Nov. 29, 1994 Description The Hitachi HN58C256 is a electrically erasable and programmable ROM organized as 32768-word x 8bit. It realizes high speed, low power consumption, and a high level of reliability, employing advanced MNOS memory technology and CMOS process and circuitry technology. It also has a 64-byte page programming function to make its erase and write operations faster. Features * * * * * * * * * * * * Single 5 V supply On-chip latches: address, data, CE, OE, WE Automatic byte write: 10 ms max Automatic page write (64 bytes): 10 ms max Fast access time: 200 ns max Low power dissipation: 20 mW/MHz typ (active) 1.1 mW max (standby) Data polling Data protection circuit on power on/off Conforms to JEDEC byte-wide standard Reliable CMOS with MNOS cell technology 105 erase/write cycles (in page mode) 10 year data retention Ordering Information Type No. HN58C256P-20 HN58C256FP-20 Access Time 200 ns 200 ns Package 600 mil 28-pin plastic DIP (DP-28) 28-pin plastic SOP (Note) (FP-28D) HN58C256 Series Pin Arrangement HN58C256P/FP Series A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 (Top View) VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Pin Description Pin Name A0 - A14 I/O0 - I/O7 OE CE WE VCC VSS Function Address Input/output Output enable Chip enable Write enable Power (+5 V) Ground 2 HN58C256 Series Block Diagram I/O0 VCC VSS OE CE WE Control Logic and Timing I/O7 High Voltage Generator I/O Buffer and Input Latch A0 A5 Address Buffer and Latch A6 A14 Y Decoder Y Gating X Decoder Memory Array Data Latch Mode Selection Pin Mode Read Standby Write Deselect Write inhibit Data polling Note: X = Don't care CE (20) VIL VIH VIL VIL X X VIL OE (22) VIL X VIH VIH X VIL VIL WE (27) VIH X VIL VIH VIH X VIH I/O (11 - 13, 15 - 19) Dout High-Z Din High-Z -- -- Data out (I/O7) 3 HN58C256 Series Absolute Maximum Ratings Parameter Supply voltage Input voltage *1 *3 *1 Symbol VCC Vin Topr Tstg Value -0.6 to +7.0 -0.5 to +7.0 0 to +70 -55 to +125 *2 Unit V V C C Operating temperature range Storage temperature range Notes: 1. With respect to V SS 2. Vin min = -3.0 V for pulse width 50 ns 3. Including electrical characteristics and data retention. Recommended DC Operating Conditions Parameter Supply voltage Input voltage Symbol VCC VIL VIH Operating temperature Topr Min 4.5 -0.3 2.2 0 Typ 5.0 -- -- -- Max 5.5 0.8 VCC + 1 70 Unit V V V C DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%) Parameter Input leakage current Output leakage current VCC current (standby) Symbol I LI I LO I CC1 I CC2 VCC current (active) I CC3 Min -- -- -- -- -- -- Input low voltage Input high voltage Output low voltage Output high voltage Note: VIL VIH VOL VOH -0.3 *1 2.2 -- 2.4 Typ -- -- -- -- -- -- -- -- -- -- Max 2 2 200 1 12 30 0.8 Unit A A A mA mA mA V Test Conditions VCC = 5.5 V, Vin = 5.5 V VCC = 5.5 V, Vout = 5.5/0.4 V CE = VCC CE = VIH Iout = 0 mA, Duty = 100%, Cycle = 1 s at VCC = 5.5 V Iout = 0 mA, Duty = 100%, Cycle = 200 ns at VCC = 5.5 V VCC + 1 V 0.4 -- V V I OL = 2.1 mA I OH = -400 A 1. VIL min = -1.0 V for pulse width 50 ns 4 HN58C256 Series Capacitance (Ta = 25C, f = 1 MHz) Parameter Input capacitance *1 *1 Symbol Cin Cout Min -- -- Typ -- -- Max 6 12 Unit pF pF Test Conditions Vin = 0 V Vout = 0 V Output capacitance Note: 1. This parameter is periodically sampled and not 100 % tested. AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10 %) Test Conditions * * * * Input pulse levels : 0.4 V to 2.4 V Input rise and fall time : 20 ns Output load : 1TTL Gate +100 pF Reference levels for measuring timing Inputs : Outputs: 0.8 V and 2.0 V Read Cycle Parameter Address to output delay CE to output delay OE to output delay Address to output hold OE, CE high to output float Note: *1 Symbol t ACC t CE t OE t OH t DF Min -- -- 10 0 0 Max 200 200 90 -- 70 Unit ns ns ns ns ns Test Conditions CE = OE = VIL, WE = VIH OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = VIL, WE = VIH 1. t DF is defined at which the outputs achieve the open circuit condition and are no longer driven. 5 HN58C256 Series Read Timing Waveform Address t ACC CE tCE OE tOE WE High tDF tOH Data Out Data Out Valid 6 HN58C256 Series Write Cycle Parameter Address setup time Address hold time CE to write setup time (WE controlled) CE hold time (WE controlled) WE to write setup time (CE controlled) WE hold time (CE controlled) OE to write setup time OE hold time Data setup time Data hold time WE pulse width (WE controlled) CE pulse width (CE controlled) Data latch time Byte lode cycle Byte lode window Write cycle time Write start time Symbol t AS t AH t CS t CH t WS t WH t OES t OEH t DS t DH t WP t CW t DL t BLC t BL t WC t DW Min*1 0 150 0 0 0 0 0 0 100 0 150 150 200 0.35 100 -- 150 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- 30 -- 10 -- *2 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s ms ns Test Conditions Notes: 1. Use this device in longer cycle than this value. 2. t WC must be longer than this value unless polling technique is used. This device automatically completes the internal write operation within this value. 7 HN58C256 Series Byte Write Timing Waveform (WE Controlled) t WC Address t CS CE t AS tWP WE t OES OE t DS Din t DH t OEH t BL t AH t CH Byte Write Timing Waveform (CE Controlled) Address t WS CE t AS WE t OES OE t DS Din t DH t OEH t AH t CW t WH t BL t WC Page Write Timing Waveform (1) (WE Controlled) 8 HN58C256 Series Address A6 to A14 Address A0 to A5 t AS WE t CS CE t OES t AH t WP t DL t CH t BLC t BL t WC t DH t OEH OE t DS Din 9 HN58C256 Series Page Write Timing Waveform (2) (CE Controlled) Address A6 to A14 Address A0 to A5 t AS CE t WS WE t OES OE t AH t CW t DL t WH t BLC t BL t WC t DH t OEH t DS Din 10 HN58C256 Series Data Polling Timing Waveform Address An An CE WE t BL OE t OE I/O7 Din X Dout X t WC Dout X t DW t OES Functional Description Automatic Page Write Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 s of the preceding rising edge of WE. When CE or WE is high for 100 s after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. Data Polling Data polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM is performing a write operation. WE, CE Pin Operation During a write cycle, addresses are latched by the falling edge of rising edge of WE or CE. Write/Erase Endurance and Data Retention Time The endurance is 105 cycles in case of the page programming and 104 cycles in case of byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page- WE or CE, and data is latched by the 11 HN58C256 Series programmed less than 104 cycles. Data Protection 1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this phenomenon, this device has a noise cancelation function that cuts noise if its width is 20 ns or less in program mode. Be careful not to allow noise of a width of more than 20 ns on the control pins. WE CE 5V 0V 5V OE 0V 20 ns max 12 HN58C256 Series 2. Data Protection at VCC On/Off When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state. VCC CPU RESET * Unprogrammable * Unprogrammable * The EEPROM should be kept in unprogrammable state during VCC on/off by using CPU RESET signal. In addition, when VCC is turned on or off, the input level of control pins must be held as shown in the table below. CE OE WE X: VCC: VSS : VCC X X X VSS X X X VCC Don't care. Pull-up to V CC level. Pull-down to VSS level. 13 HN58C256 Series Package Dimensions HN58C256P Series (DP-28) Unit: mm 28 35.60 36.50 Max 15 13.40 14.60 Max 1 1.90 Max 1.20 14 2.54 Min 5.70 Max 15.24 0.51 Min 0.25 - 0.05 0 - 15 + 0.11 2.54 0.25 0.48 0.10 HN58C256FP Series (FP-28D) Unit: mm 18.30 18.75 Max 28 15 8.40 2.50 Max 1 1.12 Max 14 + 0.08 0.17 - 0.07 11.80 0.30 1.70 0 - 10 1.27 0.40 - 0.05 + 0.10 0.20 0.10 1.00 0.20 0.20 M 0.15 14 |
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